Design and Analysis of Compressor based Dadda tree Multiplication

A multiplié is one of the key hardware blocks in most digital signal processing (DSP) systems. Typical DSP applications where a multiplier plays an important role include digital filtering, digital communications and spectral analysis. Many current DSP applications are targeted at portable, batteryoperated systems, so that power dissipation becomes one of the primary design constraints. There are several multipliers available to increase the performance level in the design field. Row bypassing multiplier with adaptive hold logic is used to reduce the power and area. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, this architecture can be applied to a columnor row-bypassing multiplier. This architecture increased delay. To overcome An appropriate design of an approximate compressor, multipliers can be designed for DSP applications. These multipliers offer significant advantages in terms of both circuitlevel and error figures of merit. The Dadda tree multiplier designed using 4:2 compressor in the proposed design to be useful in other arithmetic circuits for applications in which inexact computing can be used.